Very often in digital communication circuits it is required to generate a clock signal whose frequency (f2) is related to the frequency (f1) of another clock signal. In other words we have: f2=f1·K=f1·N/M where N<M; N and M do not have any common factors. An example of an application in which two related clocks are used is a Forward Error Correction (FEC) circuit. Typically, a FEC adds an overhead of typically M/N clock cycles. Then any circuit after the FEC will use a clock frequency of f1 and the circuits before the FEC will use a clock frequency of f2=f1·N/M.
However, as in the above example, the ratio of f2 over f1 is not an integer. One prior art approach to generate that clock is to use a phase locked loop (PLL) 100, as shown on FIG. 1. The circuit 100 includes a phase detector 103, a loop filter 104 and a voltage controlled oscillator 105 arranged as well known in the art. The frequency f1 is first divided by M in block 101 (which can be a frequency divider or other known device) and then multiplied by N in the loop 102. The disadvantages of this approach are that PLLs use analog circuits which require additional components to interface with digital circuitry and analog circuits can be sensitive to temperature variations, etc., and generally are attendant with additional cost.
Another prior art approach is to use a gapped clock circuit 200 as shown in FIG. 2. The circuit includes a gap logic circuit 201; a flip-flop 202 and an “OR” gate 203. In this circuit, the gap logic 201 is a state machine that generates a logic signal called “Gap” such that, for each period of M clock cycle, the “Gap” signal is low for N clock cycles and high for the rest of the time. Then the output frequency is f2=f1·N/M.
The disadvantage of this circuit is that it requires the use of a gated clock, which is not desirable in a digital circuit. The timing requirement at the input of the “OR” gate 203 are very critical. If the timing requirements are not addressed, glitches could occur at the output which could cause a malfunction and generate an output clock that fails to provide the N/M ratio.
Another prior art approach is to use a Direct Digital Synthesis (DDS) circuit 300 as shown in FIG. 3. In this circuit, a register 301 acts as an accumulator and is clocked with a frequency f1, and it adds N to its previous value by adder 303. Since the accumulator uses B bits, it will overflow when it reaches C≧2B, so it is in fact a modulo C accumulator and thus can only be changed in parallel with a corresponding accumulator and is limited in the values it can assume. The output of the register is provided to a comparator 302 clocked by f1 and produces an output frequency of f2=f1·N1/C, with the restriction of: N1≦C/2 and N1 being an integer.
However, to accomplish a ratio of N/M, the equation N1/C=N/M, is solved for N1 which is the only variable parameter, since the circuit uses a fixed or constant term C, N1=N·C/M. But in many cases N1 will not be an integer, so it will not be feasible to generate exactly f2. The disadvantage of this circuit is that C is not programmable, and thus the circuit 300 cannot generate all the possible values of N/M. For example, if C were 8 corresponding to a three bit accumulator, ratios of 1/8, 2/8, and 3/8 would be possible, however ratios of 3/16 and 5/16 that lie between 1/8 and 3/8, to list just a few, would not be possible.
Therefore there is a need to obviate the disadvantages of the prior art and provide a digital circuit for generating a clock signal that is N/M of another clock signal, where both N and M are selectable.
It is an object of this disclosure to present a novel circuit and method for generating a clock signal that is a function of a selectable ratio N/M.
It is also an object of the disclosure to present a novel gateless digital circuit for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N≦M/2. The gateless digital circuit having a counter, a register and an adder operable connected to generate the second clock, and both N and M are independently selectable.
It is further an object of the disclosure to present a novel improved direct digital synthesizer for generating a clock signal with a frequency of N1/M1 of a first clock frequency. The direct digital synthesizer having an adder, register and comparator, wherein the register and comparator are driven by the first clock, the adder adds N1 and the output of the register and outputs the sum to the register which outputs B bits into the comparator and wherein N is selectable. The novel improvement having a modulo M circuit between the adder and the register and replacing the fixed comparator of M1 with a variable M comparator, where M is selectable.
It is still an object of the disclosure to present a novel digital circuit for generating a second frequency clock from a first frequency clock where the second frequency is a ratio N/M of the first frequency, where N and M are adjustable integers, N≦M/2 and M<2B. The digital circuit having an adder, one input being N and the other input from a register; a modulo M function, the function receiving an adder output; the register clocked by the first frequency clock and receiving the modulo M output, and, a comparator clocked by the first frequency clock, the comparator receiving the register output and outputting the second frequency clock. The adder, modulo M function, register and comparator having a B bit capacity.
It is again an object of the disclosure to present a novel digital circuit for generating a sine wave of a second frequency from a first frequency clock where the second frequency is a ratio N/M of the first frequency, where N and M are adjustable integers, N≦M/2 and M<2B. The digital circuit having an adder with one input being N and the other input from a register; a modulo M function, the function receiving an adder output; the register clocked by the first frequency clock and receiving the modulo M output, and, a look up table receiving the register output and outputting a corresponding magnitude to create the sine wave of the second frequency. The adder, modulo M function and register having a capacity of B bits.
It is another object of the present disclosure to present a novel method for digitally generating a second clock from a source clock in a digital circuit, where the frequency of the second clock is N/M times the frequency of the source clock, and N and M are selectable integers. The novel method including the steps of: selecting an integer N; selecting an integer M, where N≦M/2; determining the Modulo M of a sum and providing the Modulo M as an input to a register; outputting a second clock from a comparator if the register output is greater than M/2; adding the output of the register to N to obtain the sum; and, clocking the register and the comparator from the source clock; thereby generating a second clock from the source clock.
It is yet another object of the disclosure to present a novel digital circuit for generating a second frequency clock from a first frequency clock where the second frequency is a ratio N/M of the first frequency, where N and M are adjustable integers, N≦M/2 and 2B>M≧(2B−N). The digital circuit having an adder with one input being N and the other input from a register; a modulo M function, the function receiving an adder output; and the register clocked by the first frequency clock and receiving the modulo M output. The register outputting the second frequency clock as the most significant bit; where the adder, modulo M function and register have B bits.
These objects and other advantages of the disclosed subject matter will be readily apparent to one skilled in the art to which the disclosure pertains from a perusal or the claims, the appended drawings, and the following detailed description of the preferred embodiments.